Our processors combine the openness of RISC-V with purpose-built AI acceleration. Every architectural decision serves a single goal: delivering maximum performance per watt for machine learning workloads.
RISC-V represents a fundamental shift in processor architecture. Unlike proprietary instruction sets controlled by single vendors, RISC-V is developed through an open, collaborative process. This openness enables SABZEH to optimize at the deepest level while maintaining complete transparency with our customers.
The base RISC-V specification provides a clean, modular foundation. We extend this with custom instructions specifically designed for neural network operations, eliminating the overhead of general-purpose architectures that were never intended for AI workloads.
No per-chip royalties or annual licensing costs that inflate your total cost of ownership.
Every instruction, every register, every pipeline stage is documented and verifiable.
Add domain-specific instructions without breaking compatibility or waiting for vendor approval.
Major semiconductor companies, governments, and research institutions are adopting RISC-V.
Each NOVA processor contains hundreds of tensor cores designed specifically for matrix multiplication, the fundamental operation in neural networks. These units achieve near-theoretical peak throughput by eliminating the instruction decode and scheduling overhead present in general-purpose cores. Native support for INT8, FP16, BF16, and FP32 precision allows optimal precision selection for each layer of your model.
Neural networks exhibit access patterns fundamentally different from traditional applications. Our memory subsystem is designed around these patterns, with large on-chip SRAM buffers that hold entire transformer attention matrices, eliminating costly off-chip memory accesses. A novel prefetch engine predicts data requirements based on network topology, ensuring compute units are never starved.
Modern AI workloads increasingly require multi-chip configurations. Our SerDes-based interconnect provides 800Gbps bandwidth between chips with latency measured in nanoseconds. Collective operations like AllReduce are implemented in dedicated hardware, achieving near-linear scaling efficiency up to thousands of chips in distributed training scenarios.
Beyond standard RISC-V vector operations, our Matrix Extension adds native support for 2D tile operations. A single instruction can compute an 8x8 or 16x16 matrix multiply-accumulate, dramatically reducing instruction overhead for convolution and attention layers.
Transformer models spend the majority of compute time in attention mechanisms. We've implemented FlashAttention-style algorithms directly in hardware, computing attention scores with optimal memory access patterns and no intermediate materialization.
Non-linear activation functions are ubiquitous in neural networks but expensive to compute. Dedicated hardware units implement GELU, SiLU, Softmax, and LayerNorm with single-cycle throughput, eliminating the performance penalty of these operations.
Production models are often pruned to reduce computational requirements. Our sparsity engine detects and skips zero values at runtime, achieving effective throughput improvements of up to 4x for appropriately structured sparse models.
Traditional cache hierarchies optimize for temporal and spatial locality assumptions that don't hold for neural networks. Weights are accessed once per inference, activations flow forward through layers, and attention patterns span the entire sequence length.
Our memory system is purpose-built for these patterns. Large on-chip SRAM buffers can hold entire layer weights, eliminating repeated off-chip fetches. A software-managed scratchpad allows explicit control over data placement, enabling optimal tiling strategies for large models.
The result is 85% sustained memory bandwidth utilization compared to 40-50% typical in conventional GPU architectures. This efficiency directly translates to higher throughput and lower latency for your AI workloads.
Secure boot chain validates firmware integrity from power-on through application launch. Tamper detection mechanisms protect against physical attacks on the device.
AES-256 encryption protects data at rest in HBM. Memory controllers perform encryption and decryption transparently with minimal performance impact.
Isolated execution environments protect sensitive model weights and inference data from other workloads sharing the same processor.
Complete RTL documentation enables security verification by your team or third-party auditors. No black boxes or hidden functionality.
Hardware performance means nothing without software that can utilize it. SABZEH provides a complete software stack from low-level drivers through high-level framework integrations.
Our compiler automatically maps standard model representations to SABZEH hardware, optimizing for data layout, operation fusion, and memory placement. Framework integrations for PyTorch and TensorFlow allow you to run existing models without modification.
Access detailed architecture specifications, performance benchmarks, and integration guides. Our engineering team is available to discuss your specific requirements.